Effective Coding with VHDL

Principles and Best Practice

by Jasinski

ISBN: 9780262334822 | Copyright 2016

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This book addresses an often-neglected aspect of the creation of VHDL designs. A VHDL description is also source code, and VHDL designers can use the best practices of software development to write high-quality code and to organize it in a design. This book presents this unique set of skills, teaching VHDL designers of all experience levels how to apply the best design principles and coding practices from the software world to the world of hardware. The concepts introduced here will help readers write code that is easier to understand and more likely to be correct, with improved readability, maintainability, and overall quality.

After a brief review of VHDL, the book presents fundamental design principles for writing code, discussing such topics as design, quality, architecture, modularity, abstraction, and hierarchy. Building on these concepts, the book then introduces and provides recommendations for each basic element of VHDL code, including statements, design units, types, data objects, and subprograms. The book covers naming data objects and functions, commenting the source code, and visually presenting the code on the screen. All recommendations are supported by detailed rationales. Finally, the book explores two uses of VHDL: synthesis and testbenches. It examines the key characteristics of code intended for synthesis (distinguishing it from code meant for simulation) and then demonstrates the design and implementation of testbenches with a series of examples that verify different kinds of models, including combinational, sequential, and FSM code. Examples from the book are also available on a companion website, enabling the reader to experiment with the complete source code.

This is the book that so many of us have been waiting for. It goes way beyond teaching VHDL language to address the principles of design. Ricardo Jasinski takes the wisdom learned from software gurus like Martin Fowler and Ward Cunningham and translates it to hardware design. It will challenge you to be a better coder and a better designer.

Philippe Faes PhD, CEO of Sigasi

Hardware designers tend to produce poorly structured VHDL while software designers often do not adequately consider resource constraints of size, speed, and real-time response. This sorely needed book shows readers how to implement and verify projects that not only meet the hardware functionality requirements but do so with concise, readable, and reusable VHDL.

Donald W. Bouldin Professor Emeritus of Electrical Engineering and Computer Science, University of Tennessee
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Contents (pg. v)
Preface (pg. xiii)
Part I Design Principles (pg. 1)
1 A VHDL Refresher (pg. 3)
1.1 Why This Book? (pg. 3)
1.2 What Is VHDL? (pg. 4)
1.3 Levels of Abstraction in Digital Systems (pg. 7)
1.4 A Summary of VHDL (pg. 9)
1.5 VHDL-2008 (pg. 31)
2 Design and Architecture (pg. 35)
2.1 What Is Design? (pg. 35)
2.2 Quality Measures (pg. 37)
2.3 Architecture (pg. 50)
3 Design Challenges (pg. 53)
3.1 Complexity (pg. 53)
3.2 Changes (pg. 55)
3.3 Dependencies (pg. 56)
3.4 Duplicate Information (pg. 57)
3.5 Technical Debt (pg. 58)
3.6 Your Wetware (pg. 60)
4 Design Principles (pg. 63)
4.1 Modularity (pg. 63)
4.2 Abstraction (pg. 69)
4.3 Hierarchy (pg. 74)
4.4 Loose Coupling (pg. 78)
4.5 Strong Cohesion (pg. 81)
4.6 The Single Responsibility Principle (pg. 83)
4.7 Orthogonality (pg. 84)
4.8 Single Source of Truth (The DRY Principle) (pg. 86)
Part II Basic Elements of VHDL (pg. 89)
5 Analysis, Elaboration, and Execution (pg. 91)
5.1 VHDL in the System Design Flow (pg. 91)
5.2 The Design Processing Flow (pg. 93)
5.3 Overview of the Analysis and Elaboration Process (pg. 96)
5.4 Detailed View of the Analysis Phase (pg. 98)
5.5 Detailed View of the Elaboration Phase (pg. 104)
5.6 The Execution Phase (pg. 107)
6 VHDL Design Units (pg. 113)
6.1 Design Units (pg. 113)
6.2 Design Libraries and Library Units (pg. 121)
6.3 Guidelines and Recommendations for VHDL Design Units (pg. 123)
7 Statements, Declarations, and Expressions (pg. 129)
7.1 Statements (pg. 129)
7.2 Declarations (pg. 132)
7.3 Expressions (pg. 140)
7.4 Guidelines and Recommendations for Statements, Declarations, and Expressions (pg. 142)
8 Operators, Operands, and Attributes (pg. 147)
8.1 Operators (pg. 147)
8.2 Operands (pg. 158)
8.3 Attributes (pg. 172)
8.4 Guidelines and Recommendations for Operators, Operands, and Attributes (pg. 180)
Part III Statements (pg. 185)
9 Concurrent Statements (pg. 187)
9.1 Introduction (pg. 187)
9.2 The process Statement (pg. 188)
9.3 The Concurrent Procedure Call Statement (pg. 203)
9.4 The Component Instantiation Statement (pg. 205)
9.5 The generate Statement (pg. 209)
9.6 Other Concurrent Statements (pg. 217)
10 Sequential Statements (pg. 223)
10.1 Control Structures (pg. 223)
10.2 The if Statement (pg. 224)
10.3 The case Statement (pg. 230)
10.4 Loops (pg. 234)
10.5 The wait Statement (pg. 246)
10.6 The assert Statement (pg. 251)
10.7 The null Statement (pg. 253)
11 Assignment Statements (pg. 255)
11.1 Kinds of Assignments in VHDL (pg. 255)
11.2 Assignment Sources and Targets (pg. 265)
11.3 Assignments with Timing and Delay (pg. 269)
11.4 Force and Release Assignments (pg. 272)
Part IV Types and Objects (pg. 277)
12 Categories of Types in VHDL (pg. 279)
12.1 Overview of Data in VHDL (pg. 279)
12.2 VHDL Type Hierarchy (pg. 286)
12.3 Subtypes (pg. 305)
12.4 Resolved Types (pg. 309)
13 Predefined and User-Defined Types (pg. 313)
13.1 Predefined and Standard Types (pg. 313)
13.2 Types and Packages for Integer Values and Operations (pg. 324)
13.3 Converting between Types (pg. 329)
13.4 Abstract Data Types (pg. 335)
13.5 Other Recommendations on Using Types (pg. 340)
14 VHDL Data Objects (pg. 345)
14.1 Constants (pg. 345)
14.2 Variables (pg. 349)
14.3 Signals (pg. 352)
14.4 Signals versus Variables (pg. 356)
14.5 Shared Variables (pg. 359)
14.6 Files (pg. 362)
14.7 Object Initial Values (pg. 367)
Part V Practical Coding Recommendations (pg. 369)
15 Excellent Routines (pg. 371)
15.1 What Is a Routine? (pg. 371)
15.2 Why Use Routines? (pg. 372)
15.3 Functions versus Procedures (pg. 375)
15.4 Writing Great Routines (pg. 379)
15.5 Parameters (pg. 386)
15.6 Where Should Routines Go? (pg. 399)
16 Excellent Names (pg. 401)
16.1 How Long Should a Name Be? (pg. 401)
16.2 General Naming Guidelines (pg. 405)
16.3 Guidelines for Naming Data Objects (pg. 409)
16.4 Guidelines for Naming Routines (pg. 415)
16.5 Guidelines for Naming Other VHDL Constructs (pg. 419)
17 Excellent Comments (pg. 429)
17.1 Comments: Good or Bad? (pg. 429)
17.2 Basic Principles (pg. 430)
17.3 Types of Comments (pg. 432)
17.4 Comment Layout (pg. 441)
17.5 Commenting Guidelines (pg. 445)
17.6 Self-Documenting Code (pg. 459)
18 Excellent Style (pg. 461)
18.1 Programming Style (pg. 461)
18.2 Code Layout (pg. 464)
18.3 Indentation (pg. 471)
18.4 Paragraphs of Code (pg. 478)
18.5 Line Length (pg. 479)
18.6 Spaces and Punctuation (pg. 483)
18.7 Letter Case (pg. 485)
18.8 Other Layout and Style Recommendations (pg. 487)
Part VI Synthesis and Testbenches (pg. 489)
19 Synthesis (pg. 491)
19.1 Introduction (pg. 491)
19.2 What Is the Difference? (pg. 492)
19.3 Creating Synthesizable Designs (pg. 497)
19.4 Inferring Hardware Elements (pg. 500)
19.5 Initialization and Reset (pg. 516)
19.6 Pragmas (pg. 518)
20 Testbenches (pg. 523)
20.1 Introduction (pg. 523)
20.2 Example #1: Testbench for a Combinational Circuit (pg. 530)
20.3 Example #2: Testbench for a Clocked Circuit (pg. 541)
20.4 Example #3: Testbench for an FSM (pg. 547)
20.5 Example #4: Testbenches with File I/O (pg. 555)
20.6 Random Stimulus and Functional Coverage (pg. 559)
20.7 Example #5: Testbench with Random Stimulus and Functional Coverage (pg. 561)
20.8 Example #6: FSM Transition Coverage (pg. 566)
20.9 Conclusion (pg. 572)
Notes (pg. 575)
Bibliography (pg. 583)
Index (pg. 585)

Ricardo Jasinski

Ricardo Jasinski is Founder and Lead Developer at Solvis Ltd.


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