## Circuit Design with VHDL, 3e

by Pedroni

### Instructor Requests

A completely updated and expanded comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard circuits.

This comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard circuits has been completely updated and expanded for the third edition. New features include all VHDL-2008 constructs, an extensive review of digital circuits, RTL analysis, and an unequaled collection of VHDL examples and exercises. The book focuses on the use of VHDL rather than solely on the language, with an emphasis on design examples and laboratory exercises.

The third edition begins with a detailed review of digital circuits (combinatorial, sequential, state machines, and FPGAs), thus providing a self-contained single reference for the teaching of digital circuit design with VHDL. In its coverage of VHDL-2008, it makes a clear distinction between VHDL for synthesis and VHDL for simulation. The text offers complete VHDL codes in examples as well as simulation results and comments. The significantly expanded examples and exercises include many not previously published, with multiple physical demonstrations meant to inspire and motivate students.

The book is suitable for undergraduate and graduate students in VHDL and digital circuit design, and can be used as a professional reference for VHDL practitioners. It can also serve as a text for digital VLSI in-house or academic courses.

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Contents (pg. v)
Preface (pg. xv)
Acknowledgments (pg. 2)
1. Review of Combinational Circuits (pg. 1)
1.1 Combinational Circuits (pg. 1)
1.2 Fundamental Logic Gates (pg. 2)
1.3 Chain-Type versus Tree-Type Structures (pg. 3)
1.4 Examples of Combinational Logic Circuits (pg. 4)
1.4.1 Multiplexer (pg. 4)
1.4.3 Parity Detector (pg. 6)
1.4.4 Priority Encoder (pg. 6)
1.4.5 Binary-to-BCD Converters (pg. 6)
1.5 Examples of Combinational Arithmetic Circuits (pg. 10)
1.5.5 Subtracters (pg. 13)
1.5.6 Incrementer, Decrementer, and Two’s Complementer (pg. 14)
1.5.7 Parallel Multiplier (pg. 14)
1.5.8 Comparators (Equality and Greater-than/Equal-to) (pg. 14)
1.5.9 Arithmetic Logic Unit (pg. 15)
1.6 Binary Arithmetic (pg. 16)
1.6.1 Carry Bit and Overflow Flag (pg. 16)
1.6.2 Unsigned Integer Arithmetic (pg. 17)
1.6.3 Signed Integer Arithmetic (pg. 19)
1.6.4 Extension, Truncation, Rounding, and Saturation (pg. 21)
1.6.5 Floating-Point Arithmetic (pg. 24)
2. Review of Sequential Circuits (pg. 29)
2.1 Sequential Circuits (pg. 29)
2.2 Latches (pg. 29)
2.3 Flip-Flops (pg. 31)
2.4 Glitch Analysis and Prevention (pg. 34)
2.5 Register Transfer Level of Abstraction (pg. 35)
2.6 Initial Examples of Sequential Circuits (pg. 36)
2.6.1 Shift Registers (pg. 36)
2.6.2 Synchronous Modulo-2N Counters (pg. 37)
2.6.3 Synchronous Modulo-M Counters (pg. 38)
2.6.4 Asynchronous Counters (pg. 38)
2.6.5 Gray, Johnson, and One-Hot Counters (pg. 39)
2.6.6 Signal Generators (pg. 41)
2.6.7 Clock Dividers (pg. 41)
2.6.8 Timers and Sequential Binary-to-BCD Converters (pg. 41)
2.6.9 Tapped Delay Line (pg. 41)
2.7 Clock Division (pg. 42)
2.7.1 Common Clock Division Cases (pg. 42)
2.7.2 Clock Division by Any Integer with Symmetric Phase (pg. 43)
2.7.3 The Cost of Clock Division by an Even Integer (pg. 44)
2.7.4 Breaking a Large Clock Divider into Smaller Serial Clock Dividers (pg. 46)
2.8 Clock Multiplication and Phase-Locked Loops (PLLs) (pg. 46)
2.9 Asynchronous Data and Synchronizers (pg. 48)
2.9.1 Clock-Domain Crossing (pg. 49)
2.9.2 A Practical Example: Frequency Meters (pg. 49)
2.9.3 Dealing with Reset (pg. 52)
2.10 Clock Gating (pg. 53)
2.11 Additional Examples of Sequential Circuits (pg. 54)
2.11.1 One-Shot and Pulse-Capturer Circuits (pg. 54)
2.11.2 Switch Debouncers (pg. 55)
2.11.3 Reference-Value Generators (pg. 58)
2.11.4 Pulse Width Modulator (pg. 59)
2.11.5 Pseudo-Random Sequence Generators (pg. 60)
2.11.6 Digital Finite Impulse Response (FIR) Filters (pg. 61)
2.11.7 Digital Infinite Impulse Response (IIR) Filters (pg. 64)
2.11.8 Serializer and Deserializer Circuits (pg. 65)
3. Review of Finite State Machines (pg. 67)
3.1 Finite State Machines (pg. 67)
3.2 State Transition Diagram and Machine Types (pg. 68)
3.3 Representing versus Implementing (pg. 70)
3.4 Moore-to-Mealy and Mealy-to-Moore Conversion (pg. 70)
3.5 Time Behavior of Moore versus Mealy Machines (pg. 71)
3.6 Choosing between Moore and Mealy Machines (pg. 73)
3.7 Transition Types (pg. 74)
3.8 Incorrect State Transition Diagrams (pg. 75)
3.9 Safe State Machines (pg. 78)
3.10 Fundamental Hardware Architectures for FSMs (pg. 78)
3.11 Encoding Styles (pg. 79)
3.12 Fundamental Design Technique for FSMs (pg. 79)
3.13 State Machine Categories (pg. 82)
3.14 Dealing with Time (pg. 83)
3.15 Dealing with Repetitive States (pg. 85)
3.16 Pointer-Based FSM Implementation (pg. 86)
3.17 Dealing with Recursivity (pg. 86)
3.18 Number of Flip-Flops in FSMs (pg. 88)
3.19 Examples of Category 1 (Regular) State Machines (pg. 88)
3.19.1 Arbiter (pg. 89)
3.19.2 Garage Door Controller (pg. 89)
3.19.3 Datapath Control for a Greatest Common Divisor (pg. 90)
3.20 Examples of Category 2 (Timed) State Machines (pg. 93)
3.20.1 Car Alarm (pg. 93)
3.20.3 Serial Peripheral Interface for an A/D Converter (pg. 95)
3.21 Examples of Category 3 (Recursive) State Machines (pg. 96)
3.21.1 SRAM Memory Interface (pg. 97)
3.21.2 Datapath Controller for a Serial Multiplier (pg. 97)
3.21.3 Reference-Value Definer with Embedded Debouncers (pg. 99)
4. Review of Field Programmable Gate Arrays (FPGAs) (pg. 101)
4.1 Programmable Logic Devices (pg. 101)
4.2 PLD Configuration Memories (pg. 103)
4.3 PAL and PLA Devices (pg. 104)
4.4 GAL Devices (pg. 104)
4.5 CPLD Devices (pg. 105)
4.6 FPGA Devices (pg. 107)
5. Introduction to VHDL (pg. 115)
5.2 Translation of VHDL Code into a Circuit (pg. 115)
5.3 Design Flow (pg. 117)
5.4 Commercial VHDL Tools (pg. 119)
5.5 RTL Design Approach (pg. 119)
5.6 Concurrent versus Sequential Statements (pg. 119)
5.7 Lexical Elements of VHDL (pg. 120)
5.7.1 Assignment Symbols (pg. 120)
5.7.3 Bit and Bit String (pg. 121)
5.7.4 Integers (pg. 121)
5.7.5 Character and Character String (pg. 122)
5.7.6 Identifiers (pg. 122)
5.7.7 Delimiters (pg. 122)
5.7.8 Reserved VHDL Words (pg. 123)
5.8 Choosing Good Names for Your Design (pg. 123)
5.8.1 Naming an Entity Declaration (“The Design“) (pg. 124)
5.8.2 Naming an Architecture Body (pg. 124)
5.8.3 Naming Constants (pg. 124)
5.8.4 Naming Signals and Variables (pg. 125)
5.8.5 Naming Functions and Procedures (pg. 125)
5.8.6 Naming Types (pg. 126)
5.8.7 Naming Files (pg. 127)
6. Code Structure and Composition (pg. 129)
6.1 Design Units and Code Structure (pg. 129)
6.2 Libraries and Packages (pg. 130)
6.3 Packages List in the Code (pg. 134)
6.4 Entity Declaration (pg. 135)
6.5 Architecture Body (pg. 138)
6.6 Object Classes (pg. 138)
6.6.1 Constant (pg. 139)
6.6.2 Signal (pg. 140)
6.6.3 Variable (pg. 141)
6.6.4 File (pg. 142)
6.7 Generics (pg. 143)
6.8 Entity-Architecture Binding (pg. 145)
6.9 Introductory VHDL Examples (pg. 145)
7. Predefined Data Types (pg. 153)
7.1 Predefined VHDL Types (pg. 153)
7.2 Type Classes (pg. 154)
7.3 Type Declarations (pg. 156)
7.4 Subtypes (pg. 158)
7.5 A Note on Operators and Attributes (pg. 159)
7.6 Study of Predefined Data Types (pg. 159)
7.6.1 Standard Types (pg. 160)
7.6.2 Standard-Logic Types (pg. 162)
7.6.3 Unsigned and Signed Types (pg. 165)
7.6.4 Fixed-Point Types (pg. 166)
7.6.5 Floating-Point Types (pg. 168)
7.6.6 Type real (pg. 170)
7.7 Record Types (pg. 172)
7.8 Access Types, File Types, and Protected Types (pg. 173)
7.9 Aggregation, Concatenation, and Resizing (pg. 173)
7.9.1 Data Aggregation (pg. 173)
7.9.2 Data Concatenation (pg. 175)
7.9.3 Resizing Data Arrays (pg. 175)
7.10 Type Conversion (pg. 178)
7.10.1 Automatic Conversion (pg. 178)
7.10.2 Type Cast (pg. 179)
7.10.3 Type-Conversion Functions (pg. 179)
7.10.4 Strength-Stripping Functions (pg. 182)
7.11 Type-Qualification Expressions (pg. 183)
7.13 Exercises (pg. 185)
8. User-Defined Data Types (pg. 193)
8.1 Review of Synthesizable Predefined Types (pg. 193)
8.2 User-Defined Types (pg. 193)
8.2.1 Integer Types (pg. 193)
8.2.2 Enumeration Types (pg. 195)
8.2.3 Array Types (pg. 195)
8.3 Building and Addressing Complex Array Types (pg. 196)
8.3.1 Array Dimensionality (pg. 196)
8.3.2 Predefined 1D Arrays (pg. 197)
8.3.3 Building 1D × 1D Arrays (pg. 197)
8.3.4 Building 2D Arrays (pg. 198)
8.3.5 Building 1D × 1D × 1D Arrays (pg. 199)
8.3.6 Building 3D Arrays (pg. 199)
8.4 Checking and Resetting Data Arrays (pg. 199)
8.4.1 Zeroing Entire Data Arrays (pg. 200)
8.4.2 Checking Whether Data Arrays Contain Only Zeros (pg. 200)
8.5 Classical Mistakes in Assignments (pg. 201)
8.7 Exercises (pg. 208)
9. Operators and Attributes (pg. 213)
9.1 Predefined Operators (pg. 213)
9.1.1 Logical Operators (pg. 214)
9.1.2 Arithmetic Operators (pg. 218)
9.1.3 Comparison (Relational) Operators (pg. 223)
9.1.4 Shift Operators (pg. 226)
9.1.5 Concatenation Operator (pg. 227)
9.1.6 Condition Operator (pg. 227)
9.2 User-Defined Overloaded Operators (pg. 228)
9.3 Predefined Attributes (pg. 229)
9.3.1 Attributes of Scalar Types (pg. 229)
9.3.2 Attributes of Array Types and Objects (pg. 230)
9.3.3 Attributes of Signals (pg. 231)
9.3.4 Attributes of Named Entities (pg. 231)
9.4 User-Defined Attributes (pg. 232)
9.5 Synthesis Attributes (pg. 234)
9.5.1 State Machine Encoding Attributes (pg. 234)
9.5.2 Safe State Machine Attributes (pg. 235)
9.5.3 Keep-Logic Attribute (pg. 236)
9.5.4 ROM and RAM Implementation Attributes (pg. 237)
9.6 Group (pg. 237)
9.7 Alias (pg. 238)
9.8 Exercises (pg. 239)
10. Concurrent Code (pg. 243)
10.1 Concurrent Statements (pg. 243)
10.2 The when Statement (pg. 246)
10.3 The select Statement (pg. 248)
10.4 The generate Statement (pg. 249)
10.5 Component Instantiation Statements (pg. 252)
10.5.1 Component Instantiation (pg. 252)
10.5.2 Design Entity Instantiation (pg. 253)
10.6 Avoiding Multiple Assignments to the Same Signal (pg. 256)
10.7 Suggested Approaches for Arithmetic Circuits (pg. 259)
10.8 Additional Examples and Exercises (pg. 264)
11. Concurrent Code: Practice (pg. 265)
11.1 Additional Design Examples Using Concurrent Code (pg. 265)
Example 11.1. Vectors Absolute Difference Calculator (pg. 265)
Example 11.2. Programmable Combinational Delay Line (Structural) (pg. 268)
Example 11.3. Sine Calculator with Integers and ROM-Type Memory (pg. 270)
11.2 Exercises (pg. 273)
Part 1: Combinational Logic Circuits (pg. 274)
Part 2: Combinational Arithmetic Circuits (pg. 277)
Part 3: With Component Instantiation (Structural Code) (pg. 281)
12. Sequential Code (pg. 283)
12.1 Concurrent Code versus Sequential Code (pg. 283)
12.2 Detecting Clock Transitions: clk’event or rising_edge(clk)? (pg. 284)
12.3 The process Statement (pg. 285)
12.4 The if Statement (pg. 288)
12.5 The case Statement (pg. 291)
12.6 The wait Statement (pg. 294)
12.7 The loop Statement (pg. 295)
12.8 The Sequential when and select Statements (pg. 297)
12.9 Signal versus Variable (pg. 298)
12.10 More about the Updating Rule of Signals and Variables (pg. 301)
12.11 More about the Inference of Registers Rule (pg. 307)
12.12 The Problem of Combinational Loops (pg. 312)
12.13 Additional Examples and Exercises (pg. 313)
13. Sequential Code: Practice (pg. 315)
13.1 Additional Design Examples Using Sequential Code (pg. 315)
Example 13.1. Generic Tree-Type Adder Array (pg. 315)
Example 13.2. Single-Switch Debouncer (pg. 318)
Example 13.3. FIR Filter with Fixed Coefficients (pg. 320)
Example 13.4. Sequential Square-Root Calculator (pg. 322)
13.2 Exercises (pg. 326)
Part 1: Signal versus Variable (pg. 326)
Part 2: Combinational Circuits (pg. 330)
Part 3: Counters and Clock Dividers (pg. 330)
Part 4: Timers and Associated Circuits (pg. 332)
Part 5: Synchronism (pg. 337)
Part 6: Shifters (pg. 339)
Part 7: Controllers (pg. 340)
Part 8: Serial Arithmetic Circuits (pg. 343)
Part 9: Filters (pg. 347)
Part 10: With Component Instantiation (Structural Code) (pg. 347)
14. Packages and Subprograms (pg. 349)
14.1 Package (pg. 349)
14.2 Package with Generics (pg. 351)
14.3 Function (pg. 353)
14.4 Procedure (pg. 359)
14.5 Function versus Procedure Summary (pg. 363)
14.6 Subprogram with Generics and Generic Subprograms (pg. 364)
14.8 Assert and Report Statements (pg. 367)
14.9 Exercises (pg. 369)
15. The Case of State Machines (pg. 373)
15.1 The Finite State Machine Approach (pg. 373)
15.2 State Encoding Styles (pg. 375)
15.3 VHDL for Regular (Category 1) State Machines (pg. 375)
15.3.1 Hardware Architecture of Regular State Machines (pg. 376)
15.3.2 Simple Moore-to-Mealy Conversion (pg. 376)
15.3.3 VHDL Templates for Regular State Machines (pg. 378)
15.4 VHDL for Timed (Category 2) State Machines (pg. 387)
15.4.1 Hardware Architecture of Timed State Machines (pg. 387)
15.4.2 VHDL Templates for Timed State Machines (pg. 388)
15.5 VHDL for Recursive (Category 3) State Machines (pg. 395)
15.5.1 Hardware Architecture of Recursive State Machines (pg. 395)
15.5.2 VHDL Templates for Recursive State Machines (pg. 395)
15.6 Summarizing (and Simplifying) Things (pg. 402)
15.7 Exercises (pg. 402)
16. The Case of State Machines: Practice (pg. 407)
16.1 Design Examples of Regular (Category 1) State Machines (pg. 407)
16.2 Design Examples of Timed (Category 2) State Machines (pg. 412)
16.3 Design Examples of Recursive (Category 3) State Machines (pg. 416)
16.4 Exercises (pg. 421)
Part 1: Exercises with Regular FSMs (pg. 421)
Part 2: Exercises with Timed FSMs (pg. 422)
Part 3: Exercises with Recursive FSMs (pg. 425)
16.5 Exercises with SPI, I2C, and LCD Interfaces (pg. 426)
17. Additional Design Examples (pg. 427)
17.1 Additional Design Examples (pg. 427)
Example 17.1. SPI Interface for an EEPROM Device (with FSM) (pg. 428)
Example 17.2. SPI Interface for an EEPROM Device (with Pointer) (pg. 434)
Example 17.3. I2C Interface for an A/D Converter (with Pointer) (pg. 440)
Example 17.4. I2C Interface for an A/D Converter (with Pointer Built with FSM) (pg. 444)
Example 17.5 Digital Watch with Liquid Crystal Display (LCD) (pg. 447)
Example 17.6 VGA Video Interface for a Hardware-Generated Image (pg. 454)
Example 17.7 DVI Video Interface for a Hardware-Generated Image (pg. 458)
Example 17.8 TMDS 8B/10B Encoder (pg. 464)
17.2 Exercises (pg. 468)
Part 1: Exercises with SPI Protocol (pg. 468)
Part 2: Exercises with I2C Protocol (pg. 469)
Part 3: Exercises with Alphanumeric LCD (pg. 471)
Part 4: Exercises with VGA Video Driver (pg. 472)
Part 5: Exercises with DVI Video Driver (pg. 473)
18. Introduction to Simulation with Testbenches (pg. 475)
18.1 Testbenches (pg. 475)
18.2 Dealing with Time in VHDL (pg. 476)
18.3 Stimuli Generation (pg. 478)
18.4 Complete Testbenches (pg. 482)
18.5 Practical Considerations on Functional and Timing Simulations (pg. 489)
18.6 Dealing with Data Files (pg. 490)
18.7 Running Simulation with Tcl Scripts (pg. 495)
18.8 Exercises (pg. 495)
Appendix A: Vivado Tutorial (pg. 497)
Appendix B: Quartus Prime Tutorial (pg. 511)
Appendix C: ModelSim Tutorial (pg. 521)
Appendix D: Simulation Analysis and Recommendations (pg. 531)
Appendix E: Using Seven-Segment Displays with VHDL (pg. 533)
Appendix F: Serial Peripheral Interface (pg. 537)
Appendix G: I2C (Inter Integrated Circuits) Interface (pg. 541)
Appendix H: Alphanumeric LCD (pg. 545)
Appendix I: VGA Video Interface (pg. 551)
Appendix J: DVI Video Interface (pg. 555)
Appendix K: TMDS Link (pg. 559)
Appendix L: Using Phase-Locked Loops with VHDL (pg. 563)
Appendix M: List of Enumerated Examples and Exercises (pg. 571)
Bibliography (pg. 581)
Index (pg. 583)

#### Volnei A. Pedroni

Volnei A. Pedroni is Professor of Electrical Engineering at Caltech and UTFPR (Federal University of Technolgy–Paraná). He is the author of Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog) (MIT Press).

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